TPL51206

2-A Sink and Source DDR Termination Regulator

数据手册

概述
开发资源
应用
订购明细

概述

With the development of main processors in PCs and servers, more and more source double-data-rate (DDR) memories are required in the mainboard, where the input voltage becomes lower and lower, and the space limitation becomes higher and higher.

The TPL51206 is a series of 2-A sink and source DDR termination regulators specifically designed for DDR applications with heavy space limitations. The TPL51206 series of devices implements a fast loadtransient response and only requires a minimum output capacitance of 10 μF.

The TPL51206 series supports a remote-sensing function and all power requirements for DDR VTT bus termination. In addition, the TPL51206 series provides S3 and S5 control pins which can be used to control the power state in DDR applications, setting OUT to high-impedance in the S3 state (suspend to RAM) and discharging OUT and REFOUT in S4 or S5 state (suspend to disk).

The TPL51206 series is available in the thermally efficient DFN2×2-10 package with the thermal pad and supports the operating temperature range from −40°C to +125°C.

Status

Production
Rating

Industrial
Minimum Input Voltage (V)

3
Maximum Input Voltage (V)

5.5
Output Voltage (V)

Adjustable (50% of REFIN)
Accuracy (max)

±40mV
Maximum Output Current (mA)

±2000
Iq (typ) (mA)

0.89
Dropout (typ) (mV)

/
PSRR @ 1kHz (dB)

/
Noise (μVRMS)

/
Temperature Range (°C)

-40 to +125
Feature

/
Package

DFN2X2-10

开发资源

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- 日期
- Datasheet_TPL51206
  
  数据手册
  
  英文
  
  02/02/2024
  
  2-A Sink and Source DDR Termination Regulator
- Introduction to Latch-up and the Preventive Measures
  
  技术文章
  
  英文
  
  01/19/2024
- PSRR Measurement for LDO
  
  技术文章
  
  英文
  
  01/19/2024
- Application Tips on ESD-EOS
  
  技术文章
  
  英文
  
  01/19/2024
- 思瑞浦模拟产品选型册
  
  选型手册
  
  中文
  
  01/19/2024