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概述
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开发资源
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应用
概述
The 3PA1030 is a monolithic, single supply, 10-Bit, 50 MSPS analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. The 3PA1030 uses multi-stage differential pipeline architecture at 50 MSPS data rates and guarantees no missing codes over the full operating temperature range.
The input of the 3PA1030 has been designed to ease the development of both imaging and communications systems. The user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially.
The sample and hold (SHA) amplifier is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single channel inputs at frequencies up to and beyond the Nyquist rate. AC coupled input signals can be shifted to a predetermined level, with an on-board 3PEAK proprietary clamp circuit. The dynamic performance is excellent.
The 3PA1030 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application.
A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range (OTR) signal indicates an overflow condition which can be used with the most significant bit to determine low or high overflow.
The 3PA1030 can operate with a supply ranging from +2.7 V to +5.5 V, ideally suiting it for low power operation in high speed applications.
The 3PA1030 is specified over the industrial (–40° C to +85° C) temperature range.
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Status
NRND
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Rating
Industrial
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Resolution
10
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Update Rate (MSPS)
50
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CH
1
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Interface
Parallel
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VIN (V)
0~2
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DNL (LSB)
0.3
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SINAD (dB)
56.5
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VDD (V)
2.7~5.5
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Power (mW)
84
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Datum
Internal
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Package
TSSOP28
开发资源
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文档
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显示筛选器隐藏筛选器文档
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数据手册
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选型手册
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应用笔记
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技术文章
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技术参考手册
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产品简介
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解决方案参考手册
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用户指南
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快速启动指南
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勘误表
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测试报告
- 文档名称
- 类型
- 语言
- 日期
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数据手册English02/02/2024
Complete 10-Bit, 50MSPS, CMOS Analog-to-Digital Converter
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技术文章English01/19/2024
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技术文章English01/19/2024
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选型手册English01/19/2024
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应用
THEORY OF OPERATION
The 3PA1030 implements a pipelined multistage architecture to achieve high sample rate with low power. The 3PA1030 distributes the conversion over several smaller A/D sub-blocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a consequence of the distributed conversion, the 3PA1030 requires a small fraction of the 256 comparators used in a traditional flash type A/D. A sample and hold function within each of the stages permits the first stage to operate on a new input sample while the second, third and fourth stages operate on the three preceding samples.
OPERATIONAL MODES
The 3PA1030 is designed to allow optimal performance in a wide variety of imaging, communications and instrumentation applications. To realize this flexibility, internal switches on the 3PA1030 are used to reconfigure the circuit into different modes. These modes are selected by appropriate pin strapping. There are three parts of the circuit affected by this modality: the voltage reference, the reference buffer, and the analog input. The nature of the application will determine which mode is appropriate: the descriptions in the following sections, as well as Table I should assist in selecting the desired mode.
